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Continuation of Moore’s law has enabled integration of many processing elements on the same chip. Chip Multi-Processor (CMP) platforms exhibit substantial performance and energy improvements over conventional uniprocessors, and yet, provide the flexibility of general purpose computing systems. Recent demonstrations of several CMP architectures have reported very promising results on execution of intensive streaming applications on programmable architectures.

Nevertheless, lack of methodologies for efficient evaluation and exploration of architecture design choices, and productive application synthesis framework have impeded proliferation of such hardware architectures in embedded systems domain, where performance and energy consumption are the primary design concerns. To address this problem, we work toward developing a FPGA-based CMP prototyping and evaluation methodology, along with application synthesis and compilation tool set, to explore the design space and develop application-specific CMP architecture.

We aim to develop a customizable array of processors (CAP) in which, the processors are soft in that they can be customized to fit the assigned computation workload. Inclusion or exclusion of functional units, and selecting the proper architecture parameters such as cache sizes and address word width are only a few examples of customization knobs. Moreover, the interconnect architecture can be tailored to better serve a selected group of applications.

Task Assignment
Processor Assignment
Code Generation

Application Analysis
Architecture Customization
Area Estimation
Performance Estimation
Architecture Generation

Page last modified on April 15, 2008, at 03:01 AM