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Seminars are in 2211 Kemper Hall at 1:00pm every Wednesday.

DatePresenterTopic
7/29/09Soheil 
7/22/09Mohammad 
7/15/09Faisal 
7/8/09MohammadOn genetic algorithms for the packing of polygons
7/1/09Nicholas 
6/24/09SoheilOptimal simultaneous module and multivoltage assignment for low power
5/27/09MatinApplication-specific customization of parameterized FPGA soft-core processors
5/20/09Nicholas 
5/13/09MatinSystematic and Automated Multiprocessor System Design, Programming, and Implementation
5/6/09FaisalA New Method for deducing LUT input mapping in FPGAs
4/29/09SoheilRobustness in CPS applications via collaborative static analysis and dynamic monitoring
4/22/09MohammadBuffer Sharing for SDF based Applications
4/8/09NicholasTraffic Monitoring Languages
3/18/09MatinProcess Variations
3/4/09FaisalModular Dynamic Reconfiguration in Virtex FPGAs
2/25/09SoheilTwo Challenges in Embedded Systems Design: Predictability and Robustness
2/18/09MohammadThe Landscape of Parallel Computing Research
2/11/09NicholasCyber Physical Systems
2/4/09MatinParallel programming on the Cell processor
1/28/09FaisalFast Monitoring for Traffic Subpopulations (IMC-'08)
8/12/08MatinExploiting coarse-grained task, data, and pipeline parallelism in stream programs
7/25/08FaisalCapturing Router Congestion and Delay
7/18/08Matinreactive process networks
7/11/08FaisalDevavrat Shah, Sundar Iyer, Balaji Prabhakar, Nick McKeown: Maintaining Statistics Counters in Router Line Cards. IEEE Micro 22(1): 76-81 (2002)
6/27/08MatinTeleport Messaging for Distributed Stream Programs
6/20/08FaisalSGS
2/8/08SoheilA Practical Approach to Exploiting Coarse-Grained Pipeline Parallelism in C Programs
2/1/08DeanDynamic Voltage Scaling for GALS
1/25/08FaisalNetwork Traffic Classification: Algorithms and Improvements
1/18/08Po-KuanTensilica Xtensa
1/11/08MatinThroughput Analysis of Synchronous Data Flow Graphs
12/14/07FaisalNew directions in traffic measurement and accounting: Focusing on the elephants, ignoring the mice
12/7/07TrevorBuffer merging - a powerful technique for reducing memory requirements of synchronous dataflow specifications
11/16/07TonyThe Apparatus and Enabling of a Code Balanced System
11/9/07Po-KuanA Provably Good Approximation Algorithm for Power Optimization Using Multiple Supply Voltages
11/2/07MatinExploring trade-offs in buffer requirements and throughput constraints for synchronous dataflow graphs
10/26/07FaisalSoftware Synthesis for Hard Real-Time Embedded Systems with Multiple Processors
10/19/07TrevorIs Java Slow?
10/12/07Po-KuanEvaluation and Design Tradeoffs Between Circuit-Switched and Packet-Switched NoCs for Application-Specific SoCs
10/5/07MatinA Survey of Research and Practices of Network-on-Chip
9/27/07TrevorA Stream Compiler for Communication-Exposed Architectures
9/20/07FaisalProgMe: Towards Programmable Network MEasurement
9/13/07MatinPractice Talk
9/6/07FaisalAn FPGA-Based Soft Multiprocessor System for IPV4 Packet Forwarding
8/30/07SoheilSynthesis of an application-specific soft multiprocessor system
8/23/07FaisalProgrammable Network Traffic Measurement
8/9/07TrevorBRAM usage in MicroBlaze/StreamIt Applications
8/2/07Zach/JeffIntel's Threaded Building Blocks
7/26/07MatinPhased Scheduling in StreamIt
7/19/07TrevorInterconnections in Multi-core Architectures: Understanding Mechanisms, Overheads, and Scaling
7/12/07Faisalalgorithms for scalable synchronization in multi-processor architectures
6/28/07AdamHigh-Level Area Estimation for Customizable Array of Processors
Page last modified on July 07, 2009, at 06:48 PM